1. Field of the Invention
The present invention relates to semiconductor devices and methods of fabricating the same, more particularly to semiconductor devices having DRAM cells and methods of fabricating the same.
2. Description of Related Art
In general, a semiconductor device having DRAM cells comprises gate patterns and capacitors on one active region selected from a cell array region. One cell includes one gate pattern and one capacitor adjacent to the gate pattern and has one address on the cell array region. The gate pattern controls the flow of data which moves through a semiconductor substrate, and the capacitor is a place where the data are stored. One bit line pattern is formed on the active region and electrically contacts the active region. The bit line pattern is a line which allows data to be moved between the cell array region and a peripheral circuit region. There have been performed studies on a capacitor over bit-line (COB) structure together with the bit line pattern. In the COB structure, the gate pattern, the capacitor and the bit line pattern arranged on the active region are insulated from each other by an insulating layer. At this time, one of DRAM cells has one contact hole in the insulating layer so that a landing pad, which is a node of the capacitor, contacts the active region. The contact hole can include of one or more holes, and also the capacitor contact landing pad can include one or more pads in accordance with the number of the holes.
But the more a high integration of the semiconductor device is required, the more reduction in a design rule of the semiconductor device is considered. The reduction in a design rule leads to small feature size of the active region, the contact hole, the gate pattern, the bit line pattern and the capacitor with the landing pad. This makes contact resistance between the capacitor contact landing pad and the active region and resistance of the gate and bit line patterns larger and also reduces a capacitance of the capacitor. An issue of design rule reduction can be solved by using upgraded semiconductor manufacturing equipments more or less, but it is very difficult to increase a contact area between the capacitor and the landing pad. A method of forming the COB structure comprises the steps of forming a storage node interlayer insulating layer on the whole surface of a semiconductor substrate having a landing pad in an insulating layer, forming a storage node hole in the storage node interlayer insulating layer, and forming a storage node by molding a doped poly silicon layer in the storage node hole. Here, the storage node hole exposes only to an upper surface of the landing pad, and an area of the side wall of the storage node corresponds to a height of the storage node hole. Therefore, due to the reduction of the design rule, a diameter of the storage node hole gets become smaller, and a size of contact area between the storage node hole and the landing pad gets become smaller. As a result, the contact resistance between the storage node and the landing pad is higher, and the storage node may be leaned or collapsed. This causes refresh fail of the DRAM cell resulting from the high contact resistance, and physical or electrical short by the storage node.
On the other hand, U.S. Pat. No. 6,136,643 to Jeng, et al discloses a method of manufacturing a capacitor having a COB structure. According to the '643 patent, the method includes forming DRAM cells having active regions, gate patterns, bit line patterns and a capacitor of a COB structure. A third etching stopper is formed to cover side walls of the bit line patterns, a third sacrificial insulating layer exist in the bit line patterns. At this time, photolithography and etching process are performed two times to form an opening portion penetrating the third sacrificial insulating layer between bit line patterns. However, during the performance of the etching process two times, the third etching stopper can be overly etched to thereby expose the side walls of the bit line patterns. Therefore, in the process of forming a lower electrode of the capacitor, the lower electrode and the bit line patterns may form a short circuit through the opening portion.